The present invention relates to vertical power semiconductor devices such as MOSFET""s (insulated gate field effect transistors), IGBT""s (insulated gate bipolar transistors), bipolar transistors and diodes. Specifically, the present invention relates to vertical power semiconductor devices which facilitate realizing a high breakdown voltage and a high current capacity.
Semiconductor devices may be classified into lateral devices, which arrange the main electrodes thereof on one major surface and make a drift current flow in parallel to the major surface, and vertical devices, which distribute the main electrodes thereof on two major surfaces facing opposite to each other and makes a drift current flow in perpendicular to the major surfaces. In a vertical semiconductor device, a drift current flows in the thickness direction of the semiconductor chip (vertically) in the ON-state of the semiconductor device and depletion layers expand also in the thickness direction of the semiconductor chip (vertically) in the OFF-state of the semiconductor device. FIG. 13, for example, is a cross sectional view of a conventional planar-type n-channel vertical MOSFET.
Referring now to FIG. 13, the vertical MOSFET includes a drain electrode 18 on the back surface of a semiconductor chip; an n+-type drain layer 11 with low electrical resistance in electrical contact with drain electrode 18; a very resistive n-type drain drift layer 12 on n+-type drain layer 11; p-type base regions 13 formed, as channel diffusion layers, selectively in the surface portion of n-type drain drift layer 12; a heavily doped n+-type source region 14 formed selectively in the surface portion of p-type base region 13; a heavily doped p+-type contact region 19 formed selectively in the surface portion of p-type base region 13 for realizing ohmic contact; a polycrystalline silicon gate electrode layer 16 above the extended portion of p-type base region 13 extended between n+-type source region 14 and n-type drain drift layer 12 with a gate insulation film 15 interposed therebetween; and a source electrode layer 17 in contact with n+-type source regions 14 and p+-type contact regions 19. Hereinafter, the very resistive drain drift layer will be referred to as an xe2x80x9cn-type drift layerxe2x80x9d or simply as a xe2x80x9cdrift layerxe2x80x9d.
In the vertical semiconductor device as described above, n-type drift layer 12 works as a layer, through which a drift current flows vertically in the ON state of the MOSFET. In the OFF-state of the MOSFET, n-type drift layer 12 is depleted by the depletion layers expanding in the depth direction thereof (vertically) from the pn-junctions between drift layer 12 and p-type base regions 13, resulting in a high breakdown voltage.
Thinning very resistive n-type drift layer 12, that is shortening the drift current path, facilitates substantially reducing the on-resistance (the resistance between the drain and the source), since the drift resistance in the ON-state of the semiconductor device is reduced. However, thinning the very resistive n-type drift layer 12 narrows the width between the drain and the base, for which depletion layers expand from the pn-junctions between drift layer 12 and p-type base regions 13. Due to the narrow expansion width of the depletion layers, the depletion electric field strength soon reaches the maximum (critical) value for silicon. Therefore, breakdown is caused at a voltage lower than the designed breakdown voltage of the semiconductor device.
A high breakdown voltage is obtained by thickening n-type drift layer 12. However, a thick n-type drift layer 12 inevitably causes high on-resistance, which further causes on-loss increase. In other words, there exists a tradeoff relation between the on-resistance (current capacity) and the breakdown voltage. The tradeoff relation between the on-resistance (current capacity) and the breakdown voltage exists in the other semiconductor devices, which include a drift layer, such as IGBT""s, bipolar transistors and diodes.
European Patent 0 053 854, U.S. Pat. No. 5,216,275, U.S. Pat. No. 5,438,215, Japanese Unexamined Laid Open Patent Application H09-266311 and Japanese Unexamined Laid Open Patent Application H10-223896 disclose semiconductor devices, which facilitate reducing the tradeoff relation between the on-resistance and the breakdown voltage. The drift layers of the disclosed semiconductor devices are formed of an alternating-conductivity-type drain drift layer including heavily doped n-type regions and heavily doped p-type regions arranged alternately. Hereinafter, the alternating-conductivity-type drain drift layer will be referred to sometimes as the xe2x80x9cfirst alternating conductivity type layerxe2x80x9d or simply as the xe2x80x9cdrain drift regionxe2x80x9d.
FIG. 14 is a cross sectional view of the vertical MOSFET disclosed in U.S. Pat. No. 5,216,275. Referring now to FIG. 14, the drift layer of the vertical MOSFET is not a uniform n-type layer (impurity diffusion layer), but a drain drift region 22 formed of thin n-type drift current path regions 22a and thin p-type partition regions 22b laminated alternately. Hereinafter, the n-type drift current path regions will be referred to as the xe2x80x9cn-type drift regionsxe2x80x9d. The n-type drift regions 22a and p-type partition regions 22b are shaped with respective thin layers extending vertically. The bottom of p-type base region 13 is connected with p-type partition region 22b. The n-type drift region 22a is extended between adjacent p-type base regions 13 and 13. Although alternating conductivity type layer 22 is heavily doped, a high breakdown voltage is obtained, since alternating conductivity type layer 22 is depleted quickly by the depletion layers expanding laterally in the OFF-state of the MOSFET from the pn-junctions extending vertically across alternating conductivity type layer 22. Hereinafter, the semiconductor device which includes drain drift region 22 formed of an alternating conductivity type layer will be referred to as the xe2x80x9csuper-junction semiconductor devicexe2x80x9d.
In the super-junction semiconductor device as described above, the breakdown voltage is high in the alternating conductivity type layer 22 (drain drift region) below p-type base regions 13 (active region of the semiconductor device) formed in the surface portion of the semiconductor chip. However, the breakdown voltage is low in the breakdown withstanding region around the alternating conductivity type layer 22 (drain drift region), since the depletion layer hardly expands outward from the pn-junction between the outermost p-type base region 13 and n-type drift region 22a or to the deep portion of the semiconductor chip, and since the depletion electric field strength soon reaches the critical value for silicon.
To obtain a high breakdown voltage in the breakdown withstanding region outside the outermost p-type base region 13, a conventional depletion electric field control means such as a guard ring formed on the breakdown withstanding region and a field plate formed on the insulation film may be employed. The breakdown voltage obtained by drain drift region 22 is higher than the breakdown voltage obtained by conventional single-layered drain drift layer 12. However, the provision of the alternating conductivity type layer makes it more difficult to obtain a higher breakdown voltage in the breakdown withstanding region by adding the conventional depletion electric field control means including the guard ring and the field plate. Therefore, the provision of the alternating conductivity type layer makes it more difficult to optimally design the additional means for correcting the depletion electric field strength in the breakdown withstanding region, and impairs the reliability of the semiconductor device. Thus, it has been impossible to fully realize the functions expectable to the super-junction semiconductor devices.
In power semiconductor devices, p-type base regions 13 are cells shaped with respective rings or respective stripes two-dimensionally to widen the channel width for obtaining a high current capacity. To reduce the wiring resistance, source electrode layer 17 is connected to n+-type source regions 14 and p+-type contact regions 19 via connection holes or connection trenches above p-type base region 13 of each cell. Source electrode layer 17 is a layer extending two-dimensionally and covering all the gate electrode layers 16 with an interlayer insulation film interposed therebetween. Although not illustrated in FIG. 14, the peripheral portion of the two-dimensionally extending source electrode layer 17 is extended outward from drain drift region 22 as a field plate. Although not illustrated in FIG. 14, gate electrode layer 16 for each cell is connected to an electrode for connecting gate electrode layers 16 to the outside (hereinafter referred to as a xe2x80x9cgate padxe2x80x9d). The gate pad is positioned in the cutout formed on a side, at a comer, or in the central portion of source electrode layer 17 on the insulation film. At least a part of the gate pad is positioned in proximity to the field plate portion of source electrode layer 17 or surrounded by source electrode layer 17.
Dynamic avalanche breakdown caused by a reverse bias voltage generated at the instance of turn off, thereat carriers are remaining, is hardly caused in the super-junction semiconductor device including drain drift region 22, since depletion layers expand quickly in drain drift region 22 at a low reverse bias voltage (around 50 V). If dynamic avalanche breakdown is caused in any portion on the side of the major surface of drain drift 22, excessive holes generated will be extracted quickly from the source power supply via the contact portions of source electrode layer 17, since any of the contact portions of source electrode layer 17 distributed to the respective cells is in proximity to the portion of alternating conductivity type layer 2, wherein the dynamic avalanche breakdown is caused.
However, when dynamic avalanche breakdown is caused below the gate pad or below the field plate, the excessive carriers are accumulated once on the boundary between the gate pad and the insulation film, and are then discharged at once toward the portion of the source electrode layer surrounding the gate pad, causing breakdown of the semiconductor device due to the generated heat and such causes. Therefore, the withstanding capability against dynamic avalanche breakdown is inevitably lower in the portions of the semiconductor chip below the gate pad than in the drain drift region, causing an unstable breakdown voltage.
In view of the foregoing, it would be desirable to provide a semiconductor device, which facilitates obtaining a breakdown voltage in the peripheral portion of the semiconductor chip higher than the breakdown voltage in the drain drift region without forming any guard ring nor any field plate on the semiconductor chip surface.
It would further be desirable to provide a semiconductor device, which facilitates preventing dynamic avalanche breakdown from causing under the gate electrode layers for controlling the ON and OFF of the semiconductor device inclusive of the gate pad or under the field plate, stabilizing the breakdown voltage thereof, and obtaining a high withstanding capability against dynamic avalanche breakdown.
The semiconductor device according to the invention is a super-junction semiconductor device including: a semiconductor chip having a first major surface and a second major surface facing opposite to the first major surface; a first electrode layer on the first major surface; a second electrode layer on the second major surface; an active region on the side of the first major surface, the active region being in electrical contact with the first electrode layer; a layer with low electrical resistance of a first conductivity type on the side of the second major surface, the layer with low electrical resistance being in electrical contact with the second electrode layer; a drain drift region between the first major surface and the layer with low electrical resistance, the drain drift region providing a vertical drift current path in the ON-state of the semiconductor device, the drain drift region being depleted in the OFF-state of the semiconductor device; the drain drift region including a first alternating conductivity type layer including vertically extending first semiconductor regions of the first conductivity type and vertically extending second semiconductor regions of a second conductivity type arranged alternately at a first pitch of repeating; and a breakdown withstanding region around the drain drift region, the breakdown withstanding region being between the first major surface and the layer with low electrical resistance, the breakdown withstanding region providing substantially no current path in the ON-state of the semiconductor device, the breakdown withstanding region being depleted in the OFF-state of the semiconductor device, the breakdown withstanding region including a second alternating conductivity type layer including vertically extending third semiconductor regions of the first conductivity type and vertically extending fourth semiconductor regions of the second conductivity type arranged alternately at a second pitch of repeating.
The structure described above is applicable to the vertical active semiconductor device which has three or more terminals. In the case of n-channel MOSFET""s, the active region thereof includes source regions and channel diffusion regions. The first electrode layer is a source electrode layer, the second electrode layer a drain electrode layer, and the third electrode layer is a gate pad for connecting gate electrode layers to the outside. In the case of bipolar transistors, the second electrode layer is an emitter or a collector, and the third electrode layer is a control electrode for switching on and off the bipolar transistors.
The semiconductor device according to the invention advantageously includes a breakdown withstanding region formed around the drain drift region, the breakdown withstanding region being between the first major surface and the layer with low electrical resistance, the breakdown withstanding region including a second alternating conductivity type layer including vertically extending third semiconductor regions of the first conductivity type and vertically extending fourth semiconductor regions of the second conductivity type arranged alternately at a second repeating pitch.
The breakdown voltage of the semiconductor device according to the invention is high, since depletion layers expand in the OFF-state of the semiconductor device from very many pn-junctions not only to the drain drift region but also to the portion of the semiconductor chip outside the drain drift region and the deep portion of the semiconductor chip near the second major surface due to the provision of the second alternating conductivity type layer with a second repeating pitch which is narrower than a first repeating pitch in the breakdown withstanding region. Since the curved electric line of force extending from the side of the active region to the layer with low electrical resistance via the breakdown withstanding region is longer than the electric line of force extending from the active region on the side of the first major surface to the layer with low electrical resistance via the drain drift region, the electric field strength in the breakdown withstanding region is lower than that in the drain drift region even when the impurity concentrations in both regions are the same. Therefore, the breakdown voltage in the breakdown withstanding region is higher than that in the drain drift region. Since a high breakdown voltage is obtained in the breakdown withstanding region of the super-junction semiconductor device including a drain drift region formed of an alternating conductivity type layer, the structure of the alternating conductivity type layer in the drain drift region is optimized easily, a super-junction MOSFET is designed more freely, and the resulting MOSFET is a practical one.
The semiconductor device according to the invention includes a third electrode layer for controlling the ON and OFF of the semiconductor device above the first major surface with an insulation film interposed therebetween, at least a part of the third electrode layer being in close proximity to the first electrode layer; and an under region below the third electrode layer for controlling the ON and OFF of the semiconductor device, the under region including a third alternating conductivity type layer including vertically extending fifth semiconductor regions of the first conductivity type and vertically extending sixth semiconductor regions of the second conductivity type arranged alternately at a third pitch of repeating; and the third pitch of repeating being narrower than the first pitch of repeating. When the third electrode layer is in close proximity to the peripheral portion of the first electrode layer, the under region below the third electrode layer includes the portion of the semiconductor chip below the peripheral portion of the first electrode layer.
The third electrode layer is positioned on the insulation film and in the cutout formed on a side, at a corner or in the central portion of the first electrode layer. At least a part of the third electrode layer is in close proximity to the first electrode layer. Since the third pitch of repeating in the third alternating conductivity type layer below the third electrode layer is narrower than the first pitch of repeating in the drain drift region, the unit area is depleted more easily in the under region than in the drain drift region. Therefore, the breakdown voltage in the under region never determines the breakdown voltage of the semiconductor device according to the invention. Since depletion layer expand more quickly in the under region than in the drain drift region when the semiconductor device is switched off, the electric field strength in the under region is relaxed and carriers are expelled to the drain drift region. Therefore, dynamic avalanche breakdown is hardly caused in the under region below the third electrode layer. Since dynamic avalanche breakdown is caused in the drain drift region, dynamic avalanche breakdown is prevented from causing in the under region, a stable breakdown voltage is obtained, and a high withstanding capability against dynamic avalanche breakdown is obtained.
Since depletion layers expand more easily in the in the under region than in the drain drift region when the third alternating conductivity type layer is doped more lightly than the first alternating conductivity type layer, dynamic avalanche breakdown is further prevented from causing in the under region below the third electrode layer. Even when the third pitch of repeating is equal to or wider than the first pitch of repeating, dynamic avalanche breakdown is prevented from causing in the under region by doping the under region more lightly than the drain drift region considering the first and third pitches of repeating.
Advantageously, the second alternating conductivity type layer is doped more lightly than the first alternating conductivity type layer. When the second alternating conductivity type layer is doped more lightly than the first alternating conductivity type layer, the breakdown voltage of the semiconductor device is determined by the first alternating conductivity type layer in the drain drift region, and dynamic avalanche breakdown is prevented from causing in the breakdown withstanding region.
Advantageously, the semiconductor device according to the invention further includes a first well region of the second conductivity type connected electrically to the first electrode layer, the first well region covering the surface of the third alternating conductivity type layer on the side of the first major surface. Since all the sixth semiconductor regions of the second conductivity type in the third alternating conductivity type layer are biased surely at a reverse bias voltage, this structure facilitates expanding depletion layers from the pn-junctions of the third alternating conductivity type layer in the depth direction of the semiconductor chip, obtaining a high breakdown voltage in the under region, and preventing dynamic avalanche breakdown from causing more surely in the under region. Therefore, the withstanding capability against dynamic avalanche breakdown is improved. If dynamic avalanche breakdown is caused in the under region, the excessive holes caused will be extracted to the first electrode layer via the first well region for hole extraction without being accumulated on the boundary between the third electrode layer and the insulation film. Therefore, the MOSFET is not broken down by the heat generated and such causes.
Since it becomes difficult to deplete the entire third alternating conductivity type layer and the electric field tends to localize to the curved side of the first well region of the second conductivity type when the first well region of the second conductivity type covers a part of the third alternating conductivity type layer on the side of the first major surface, dynamic avalanche breakdown tends to be caused on the pn-junction (boundary) between the third and first alternating conductivity type layers.
To obviate this problem, the surface of the third alternating conductivity type layer on the side of the first major surface is preferably in contact with the bottom of the first well region. This structure facilitates depleting the third alternating conductivity type layer uniformly. When the third electrode layer is positioned on a side of the first electrode layer or at a corner of the first electrode layer, any of the sides of the first well region of the second conductivity type is connected to the end portion of the first alternating conductivity type layer or the second alternating conductivity type layer. When the third electrode layer is positioned in the central portion of the first electrode layer, all the sides of the first well region of the second conductivity type are connected to the end portions of the first alternating conductivity type layer. Therefore, the pn-junction which corresponds to the boundary between the third and first alternating conductivity type layers is connected to the first well region of the second conductivity type. This structure facilitates stabilizing the breakdown voltage of the semiconductor device, since dynamic avalanche breakdown is expelled to the drain drift region and since the pn-junction which corresponds to the boundary between the third and second alternating conductivity type layers is also connected to the first well region of the second conductivity type. It is preferable to connect the outermost second semiconductor region of the second conductivity type of the first alternating conductivity type layer with the first well region of the second conductivity type. This structure facilitates adjusting the charge balance between the between the outermost second semiconductor region of the second conductivity type of the first alternating conductivity type layer and the innermost fifth semiconductor region of the first conductivity type of the third alternating conductivity type layer adjacent to each other.
Advantageously, the pn-junctions in the second alternating conductivity type layer extend in parallel to the pn-junctions in the first alternating conductivity type layer. Advantageously, the pn-junctions in the second alternating conductivity type layer extend in perpendicular to the pn-junctions in the first alternating conductivity type layer. Advantageously, the pn-junctions in the third alternating conductivity type layer extend in parallel to the pn-junctions in the first alternating conductivity type layer. Advantageously, the pn-junctions in the third alternating conductivity type layer extend in perpendicular to the pn-junctions in the first alternating conductivity type layer. Advantageously, the first through sixth semiconductor regions of the first through third alternating conductivity type layer are shaped with respective stripes in a plane parallel to the first major surface or the second major surface. Alternatively, the semiconductor regions of the first conductivity type or the semiconductor regions of the second conductivity type may be shape with respective columns positioned at the lattice points of a trigonal lattice, a tetragonal lattice or a cubic lattice. Since the area of the pn-junctions per a unit area increases, the breakdown voltage is improved. The semiconductor regions of the first conductivity type and the semiconductor regions of the second conductivity type may be continuous diffusion regions, the impurity concentration thereof distributes uniformly. Advantageously, the semiconductor regions of the first conductivity type or the semiconductor regions of the second conductivity type may be formed by connecting unit diffusion regions scattered in the semiconductor chip vertically, since the alternating conductivity type layers are formed easily. The impurity concentration is the maximum at the center of each unit diffusion region and decreasing gradually as the position is spaced apart from the center of each unit diffusion region.
Since the third electrode layer is an electrode layer for controlling the ON and OFF of the semiconductor device, the configurations described above are applicable to the vertical active semiconductor device having three or more terminals.
The configurations according to the invention applicable to the vertical passive semiconductor device having two terminals will be described below.
According to a second aspect of the invention, there is provided a semiconductor device including: a semiconductor chip having a first major surface and a second major surface facing opposite to the first major surface; a first electrode layer on the first major surface having a first peripheral portion; a second electrode layer on the second major surface; an active region on the side of the first major surface, the active region being in electrical contact with the first electrode layer; a layer with low electrical resistance of a first conductivity type on the side of the second major surface, the layer with low electrical resistance being in electrical contact with the second electrode layer; a drain drift region between the first major surface and the layer with low electrical resistance, the drain drift region providing a vertical drift current path in the ON-state of the semiconductor device, the drain drift region being depleted in the OFF-state of the semiconductor device; the drain drift region including a first alternating conductivity type layer including vertically extending first semiconductor regions of the first conductivity type and vertically extending second semiconductor regions of a second conductivity type arranged alternately at a first pitch of repeating; a breakdown withstanding region around the drain drift region, the breakdown withstanding region being between the first major surface and the layer with low electrical resistance, the breakdown withstanding region providing substantially no current path in the ON-state of the semiconductor device, the breakdown withstanding region being depleted in the OFF-state of the semiconductor device, the breakdown withstanding region including a second alternating conductivity type layer including vertically extending third semiconductor regions of the first conductivity type and vertically extending fourth semiconductor regions of the second conductivity type arranged alternately at a second pitch of repeating; an under region below the first peripheral portion of the first electrode layer, the under region including a third alternating conductivity type layer including vertically extending fifth semiconductor regions of the first conductivity type and vertically extending sixth semiconductor regions of the second conductivity type arranged alternately at a third pitch of repeating; and the third pitch of repeating being narrower than the first pitch of repeating. Whether the semiconductor device includes a third electrode layer or not is not important.
The structure described above facilitates improving the breakdown voltage below the first peripheral portion of the first electrode layer and the withstanding capability against dynamic avalanche breakdown. Advantageously, the third alternating conductivity type layer is doped more lightly than the first alternating conductivity type layer.
Advantageously, the semiconductor device further includes a first well region of the second conductivity type connected electrically to the first electrode layer, the first well region covering the surface on the side of the first major surface of the third alternating conductivity type layer. The under region below the first peripheral portion of the first electrode layer is biased surely at the reverse bias voltage. Moreover, if dynamic avalanche breakdown is caused in the under region, the carriers caused will be extracted to the first electrode layer via the first well region of the second conductivity type and the semiconductor device is prevented from being broken down.
Advantageously, the first electrode layer further includes a second peripheral portion, below which the second alternating conductivity type layer is extended. Advantageously, the semiconductor device further includes a second well region of the second conductivity type connected electrically to the first electrode layer, the second well region covering the surface on the side of the first major surface of the extended portion of the second alternating conductivity type layer extended below the second peripheral portion of the first electrode layer. The extended portion of the second alternating conductivity type layer below the second peripheral portion of the first electrode layer is biased surely at the reverse bias voltage. Moreover, if dynamic avalanche breakdown is caused in the extended portion of the second alternating conductivity type layer, the carriers caused will be extracted to the first electrode layer via the second well region of the second conductivity type and the semiconductor device is prevented from being broken down.
Advantageously, the innermost second semiconductor region (or the outermost second semiconductor region) of the first alternating conductivity type layer in contact with the outermost fifth semiconductor region (or the innermost fifth semiconductor region) of the third alternating conductivity type layer is connected to the first well region of the second conductivity type. Since the pn-junction between the second semiconductor region of the second conductivity type of the first alternating conductivity type layer and the fifth semiconductor region of the first conductivity type of the third alternating conductivity type layer is connected to the first well region of the second conductivity type, dynamic avalanche breakdown is hardly caused. Moreover, this structure facilitates adjusting the charge balance between the second semiconductor region and the fifth semiconductor region in contact with each other.
Advantageously, the outermost second semiconductor region of the first alternating conductivity type layer in contact with the innermost third semiconductor region of the second alternating conductivity type layer is connected to the second well region of the second conductivity type. Since the pn-junction between the second semiconductor region of the second conductivity type of the first alternating conductivity type layer and the third semiconductor region of the first conductivity type of the second alternating conductivity type layer is connected to the second well region of the second conductivity type, dynamic avalanche breakdown is hardly caused. Moreover, this structure facilitates adjusting the charge balance between the second semiconductor region and the fifth semiconductor region in contact with each other.